Despite the development of faster processing speeds, today's digital computer has been gradually recognized as being very unsuitable for the process requiring integrated judgment and intelligence.
The human brain is known to process data in associative memory and in parallel, and is able to recognize and memorize using partial information.
A worldwide effort is being undertaken to create a neural computer, modeling the computer after the parallel-process and the associative memory of the human brain.
About fifty kinds of the neural circuit models have been published up to now. J. J. Hopfield, in 1982, of Caltech proposed a neural network modeled after associative memory-processing and showed the possibility of constructing hardware by applying analog circuits and VLSI technologies to this neural network model (J. J. Hopfield, Proc. Natl. Acad. Sci. U.S.A., Vol. 79, PP2554.about.2558, April 1982).
Also, J. J. Hopfield, in 1986, explained an A/D converter by way of example, suggesting the model for solving the optimization problem (D. W. Tank and J. J. Hopfield, IEEE. Transactions on circuit and systems, Vol. CAS-33, No. 5, May 1986).
However, the above A/D converter circuit was unstabled due to the occurrence of two local Minima for each stage. Therefore the above A/D converter circuit had to be designed to be supplemented with a special complementary circuit in order to stabilize the circuit.
Because computer arithmetic operations are carried out by sequential addition, the time consumed during the adding process becomes significant.
Therefore adder designs of known digital circuits utilize the carry look ahead generator circuit in order to reduce the carry propagation delay time and to process the operation of each stage in a parallel manner.
Therefore, to construct a parallel adder of N-bits, the carry look ahead generator circuit of an N-bit full adder requires a gate number proportional to N.
In a VLSI implementation of this above described binary adder, the VLSI area required is proportional to the size of the number of bits in the adder. It would be desirable to reduce the required VLSI area.